二手 TERADYNE Tiger #174983 待售
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已售出
ID: 174983
Tester
Currently warehoused
Configuration:
#
# Confsim file created on: 03/18/02 13:38:06
#
# Tiger tester tigert1
#
# tigert1 is a 2 processor system
# Processor 1: 450 MHz sparc (online)
# Processor 3: 450 MHz sparc (online)
# PCI based system
# Terabus is present
# TCI is present
#
TIGER_TH 1
BACKPLANE A
# Slot Type XptA XptB Name
2 0x0000000 0
# 23 24 EMPTY
3 0x0000000 0
# 21 22 EMPTY
4 0x0000000 0
# 19 20 EMPTY
5 0x0000000 0
# 17 18 EMPTY
6 0x0000000 0
# 15 16 EMPTY
7 0x0000000 0
# 13 14 EMPTY
8 0x0000000 0
# 11 12 EMPTY
9 0x0000000 0
# 9 10 EMPTY
10 0x0000000 0
# 7 8 EMPTY
11 0x0000000 0
# 5 6 EMPTY
14 0x0000000 0
# 25 26 EMPTY
15 0x0000000 0
# 27 28 EMPTY
16 0x0000000 0
# 29 30 EMPTY
17 0x0000000 0
# 31 32 EMPTY
18 0x0000000 0
# 33 34 EMPTY
19 0x0000000 0
# 35 36 EMPTY
20 0x0000000 0
# 37 38 EMPTY
21 0x0000000 0
# 39 40 EMPTY
22 0x0264d27 0
# 41 42 QVS CC
23 0x0000000 0
# 43 44 EMPTY
1 0x026420b 0
# 3 0 ACISB-L
24 0x0264783 0
# 4 0 ACISB-R
END
#
# Up to 4 Precision AC Card Cages are allowed
#
PRECISION_AC 1
# Slot Type # Num Name
1 0x0000000 0
# EMPTY
2 0x0000000 0
# EMPTY
3 0x0000000 0
# EMPTY
4 0x0000000 0
# EMPTY
5 0x0278862 0
# TJA BOARD
6 0x0000000 0
# EMPTY
7 0x0000000 0
# EMPTY
8 0x11d2463 0
# PACS CAGE INT
END
#
# Up to 8 Universal Backplane/Synch Power Subsystem
# cages are allowed
#
# For the Synch Power Subsystem:
# Slot Type Name Instr1
# Instr2
# Ammeter
#
#
# Instr1
# - insrument connected to the first two matrix lines
# Instr2 # - insrument connected to the last two matrix lines
# Ammeter # - ammeter connection
# to AVOID errors, put NO 0 if no instrument is connected.
#
#
UB_SPS_CAGE 1
# Slot Type Num Name
1 879-802-02 0 # UB_SPS_802
2 517-301-01 0 # UB_MATRIX
3 517-301-01 0 # UB_MATRIX
4 517-301-01 0 # UB_MATRIX
5 517-301-01 0 # UB_MATRIX
6 517-301-01 0 # UB_MATRIX
7 517-301-01 0 # UB_MATRIX
8 517-301-01 0 # UB_MATRIX
9 517-301-01 0 # UB_MATRIX
10 517-301-01 0 # UB_MATRIX
11 517-301-01 0 # UB_MATRIX
12 517-301-01 0 # UB_MATRIX
13 517-301-01 0 # UB_MATRIX
14 879-925-01 0 # UB_60_V_SRC MAT 1
15 879-925-01 0 # UB_60_V_SRC DUT 1
16 879-925-01 0 # UB_60_V_SRC MAT 2
21 879-690-00 0 # UB_ASY
22 517-300-01 0
# UB_TJ300
UB_SPS_CAGE 2
# Slot Type
# Num Name
1 879-802-02 0
# UB_SPS_802
6 949-700-10 0
# UB_QVS_CAL 1
7 949-693-10 0
# UB_QVS_CTRL 22 ??
8 949-698-10 0
# UB_QVS_AM 1
9 949-698-10 0
# UB_QVS_AM 2
22 517-300-01 0
# UB_TJ300
END
CSB_CAGE 8
#Slot Type Serial
# Num Fld1 Fld2 Name
1 949-920-60 0 # HSD CSB
2 949-866-00 0 # SPLITTER
END
TIGER_TH 1
BACKPLANE B
#Slot Type Serial # Num Name
26 805-870-52 0 # PE32 128M
27 805-870-52 0 # PE32 128M
28 805-870-52 0 # PE32 128M
29 805-870-52 0 # PE32 128M
30 805-873-81 0 # QSB
35 805-870-52 0 # PE32 128M
36 805-870-52 0 # PE32 128M
37 805-870-52 0 # PE32 128M
38 805-870-52 0 # PE32 128M
39 805-873-81 0 # QSB
40 805-870-52 0 # PE32 128M
41 805-870-52 0 # PE32 128M
42 805-870-52 0 # PE32 128M
43 805-870-52 0 # PE32 128M
45 805-870-52 0 # PE32 128M
46 805-870-52 0 # PE32 128M
47 805-870-52 0 # PE32 128M
48 805-870-52 0 # PE32 128M
49 805-873-81 0
# QSB
50 805-870-70 0
# PE32 128M
51 805-870-52 0
# PE32 128M
52 805-870-52 0
# PE32 128M
53 805-870-52 0
# PE32 128M
58 805-873-03 0
# QSB HCLK
END
#
# Time Subsystem
#
TIME_SUBSYSTEM
# Board ID Name
949-782-00 Time Mux Board 1
949-782-00 Time Mux Board 2
END
#
# DC Subsystem -
#
# SRC <NUM> [1 - 13]
# (sources 1-5 are MATRIX sources 1-5
# sources 6-13 are DUT sources 1-8)
# HCU <NUM> *[1 - 4]
# REF HCU <NUM> *[1 - 4]
# HVSRC <NUM> *[1 - 4]
# PWRSRC <NUM> [1 - 4]
# DATABITS <NUM> - <NUM> [1 - 192]
#
# ** These instruments share the same seven-slot cage -- only one
instrument is allowed per slot.
#
DC_SUBSYSTEM
#
UBVI 60 1 ( 60V V/I Source in Universal Backplane 1 : slot 14)
# UBVI 60 2 ( 60V V/I Source in Universal Backplane 1 : slot 16)
# UBVI 60 6 ( 60V V/I Source in Universal Backplane 1 : slot 15)
HCU 7
HCU 8
DATABITS 1 - 48
# UB_MATRIX
#
# Testhead 1
# XPTs UB Cage Slot Type
# 1-4 1 2 Matrix
# 5-8 1 3 Matrix
# 9-12 1 4 Matrix
# 13-16 1 5 Matrix
# 17-20 1 6 Matrix
# 21-24 1 7 Matrix
# 25-28 1 8 Matrix
# 29-32 1 9 Matrix
# 33-36 1 10 Matrix
# 37-40 1 11 Matrix
# 41-44 1 12 Matrix
# 45-48 1 13 Matrix
END.
TERADYNE TIGER Final Test Equipment是一个革命性的测试解决方桉,旨在提供全面且经济高效的解决方桉,以应对电路板测试中经常遇到的难题。该系统的设计目标是减少与传统电路板测试程序相关的时间和金钱,同时提供准确、可靠和易于应用的结果。TigerFinalTestUnit由几个核心组件组成，这些组件结合在一起产生其有效和全面的性能。该机器采用集成设计环境（IDE）,允许工程师同时测试多个设计,从而节省时间和金钱。该工具还具有强大的基于扫描的测试体系结构,可用于测试高速电路和外围设备。此外,资产还配备了板载脚本引擎,可实现自定义测试脚本和自动化。该模型可以测试各种电路配置,并包括许多独特的功能,以确保准确可靠的结果。该设备提供详细的性能反馈,以支持生产和工艺产量优化,同时可以使用专门的自动化诊断工具来识别设计缺陷或板级缺陷。此外，系统还配备了先进的视觉识别单元，提供详细的二进制或模拟特征识别和提取能力。TERADYNE Tiger Final Test Machine还配备了高级通信工具，可用于访问远程资源或配置多个测试系统。软件环境是模块化的,这意味着用户可以轻松定制使用该工具的体验,以更好地满足其特定需求。此外,该资产是为开放式协作而设计的,可方便地在工程师和团队之间共享数据和结果,从而创建更高效的工作流。最后,Tiger Final Test Model提供了非凡的物有所值,因为它价格实惠,但功能强大且可靠。因此,设备提供了无与伦比的易用性,并为组织（特别是电子行业的组织）提供了全面且经济高效的最终测试解决方桉。
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